1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) having open bit lines, and more particularly to a DRAM having bidirectional global bit lines in which local bit lines connected to corresponding memory cells and separative global bit lines connected to the local bit lines are commonly connected so that data may be read from or stored in the cells in a bidirectional manner.
2. Description of the Prior Art
In general, DRAMs typically are divided into folded bit line and open bit line structures. More specifically, FIG. 1 (A) illustrates such a DRAM of an open bit line structure. A pair of local bit lines (e.g., BL1 and/BL1) ("/" typically denotes herein complementary lines or signals or active low signals) are provided at the right and left sides of sense amplifiers SA1 and SA2. Word lines WL (WL1-WLn) intersect the local bit lines and memory cells ms are serially arranged at the intersections of the local bit lines and word lines.
FIG. 1 (B) illustrates such a DRAM of a folded bit line structure. As indicated, a pair of local bit lines BL and /BL are connected to one side of sense amplifiers SA1 and SA2. Word lines WL intersect the local bit lines and memory cells ms are alternatively arranged at the intersections of local bit lines BL and/BL and word lines WL.
Moreover, as illustrated in FIG. 2, in a DRAM of such a folded bit line structure, word lines WL are connected to row decoder RC. Odd-numbered bit lines BL and/BL (i.e., BL1 and /BL1, BL3 and /BL3, . . . ) are connected to second sense amplifier and precharge circuit SA2 via switching portion 81 which is activated by way of external signal BK to separate local bit lines BL and /BL, while even-numbered bit lines BL and/BL (i.e., BL0 and /BL0, BL2 and /BL2 . . . ) are connected to first sense amplifier and precharge circuit SA1 via switching portion 80 which is activated by signal BK'. Further, cell selecting signals Y1 to Yn produced by column decoder CC are commonly connected to first and second sense amplifier and precharge circuits SA1 and SA2. Then, data in the cells selected by cell selecting signals Y1 to Yn are supplied to external circuits (not shown) through input and output lines I/O and I/O.
More specifically, as illustrated in FIG. 3, when an external row address strobe (/RAS) signal is changed from a high level to a low level, a row address is latched into an internal circuit (for example, row decoder RC) and equalizing signal EQ somewhat delayed with respect to the RAS signal then becomes a low level (see FIG. 3). Accordingly, the equalizing operation for local bit lines BL and /BL is stopped so that the local bit lines are separated from precharging voltage VBL. At this time, signals BK and BK' have a higher level than a level defined by Vcc+Vth. That is, if any one of word lines WL1 to WLn is selected by column decoder CC, then all of signals BK and BK' become a high level, while signals BK+1 and Bk-1 are changed to a low level, so that switching portions 80 and 81 are rendered conductive or turned ON. Consequently, the word line thus selected is changed to a high level by way of the row address. Accordingly, charges stored in the selected cell appear on one of local bit lines BL and /BL, so that the voltage of that local bit line is somewhat increased or decreased depending upon the charge of the cell. Under this condition, if signal SN serving as a sense amplifier enable signal becomes a high level and signal SP serving as a sense amplifier enable signal becomes a low level, then the voltage difference between the local bit lines is enlarged. As a result, the data stored in the cell is transferred to the input and output lines I/O and I/O via sense amplifier and precharge circuits SA1 and SA2.
With the DRAM of a folded bit line structure described above, however, it requires sense amplifier and precharge circuits, input and output lines, switching portions for column decoding and the switching circuit for connecting the local bit lines to the sense amplifier and precharge circuits. Accordingly, multiple FETs of sixteen or more, in addition to the word line forming area, must be connected to each pair of the local bit lines and, thus, the FETs occupy a relatively large area such as an element isolation area defined between NMOS and PMOS elements, thereby undesireably decreasing the efficiency of the cells.